This invention relates to trench-gate semiconductor devices, for example power MOSFETs (insulated-gate field-effect transistors), and their manufacture.
Published Japanese patent application Kokai JP-A-2001-24193 and its English-language abstract in Patent Abstracts of Japan describe cellular trench-gate semiconductor devices comprising active device cells in a cellular area of a semiconductor body, and a device termination structure that extends around the whole perimeter of the cellular area. The whole contents of Kokai JP-A-2001-24193 and its said English-language abstract are hereby incorporated herein as reference material.
Each active device cell has a channel-accommodating region of a second conductivity type between a surface-adjacent source region and an underlying drain region that are of a first conductivity type. An insulated gate trench accommodating the trench-gate extends from the source region through the channel-accommodating region and into the underlying drain region. The trench-gate is dielectrically coupled to the channel-accommodating region by an intermediate gate dielectric layer at sidewalls of the gate trench.
The particular device termination structures disclosed in JP-A-2001-24193 include:
an end region 4(p) of the second conductivity type having a higher doping concentration than the channel-accommodating region 8(p),
an end trench 5B that is an extension of the insulated gate trench 5A into the end region 4(p) and that accommodates an extension 7B of the trench-gate 7A,
and a conductive layer 7C that is connected to the extension of the trench-gate and extends over an intermediate insulating layer 3,6 over the end region 4(p).
As taught in JP-A-2001-24193, the end region 4(p) may be deeper or shallower than the channel-accommodating region 8(p), and the end trench 5B may be deeper or shallower than the end region 4(p). The conductive layer 7C forms an outwardly-extending field plate on the intermediate insulating layer 3,6. In these known devices, the intermediate insulating layer comprises a thick LOCOS field oxide 3 around a thinner oxide layer 6 that is present on the end region 4(p). The thick field oxide 3 is present over the outer perimeter of the end region 4(p) and over a portion of the drain region 2(n) beyond the end region 4(p). The thinner oxide layer 6 is formed simultaneously with the gate dielectric 6 in the devices of JP-A-2001-24193, after removing the trench-etch mask RE1.
It is an aim of the present invention to provide a more substantial insulating layer (preferably comprising silicon nitride) between the high-doped end region and the overlying conductive layer, and particularly to provide a thicker insulating layer that may be used in self-alignment of device features in manufacture (for example, the source region and/or an insulating capping layer with respect to the gate trench).
According to a first aspect of the invention, the resulting device is characterised in that:
the intermediate insulating layer comprises an area of a trench-etch mask (preferably comprising silicon nitride) that is of greater thickness than the gate dielectric layer,
a window extends through the trench-etch mask at a location where the end trench extends into the body and where the conductive layer is connected to the trench-gate extension, and
the conductive layer has a lateral extent that terminates in an edge on the trench-etch mask.
The area of trench-etch mask is recognisable in the final device by its window from which the end trench extends into the body. Keeping this mask area can benefit both manufacture of the device and the final device structure.
Thus, the trench-etch mask area is a better interface (than a thin gate-dielectric layer area) on which to deposit and pattern the conductive layer that is connected to the trench-gate. This is particularly important for defining an edge of the conductive layer facing the cellular area. If this edge of the conductive layer is defined by etching on a gate-dielectric layer area (as in JP-A-2001-24193), there is a risk of etching through (or otherwise damaging) the thin gate-dielectric layer area, so degrading the insulation on the high-doped end region and possibly also in other areas (for example, active device cell areas). These areas are protected in the manufacture of a device in accordance with the invention, by keeping the trench-etch mask during this stage. Keeping the respective trench-etch mask area on the end region in the final device also provides a better insulation scheme, which is beneficial in different scenarios.
In one scenario, the end structure extends between two groups of active device cells as a stripe that includes a metal track to reduce the gate connection resistance for these groups of active device cells. Such a scheme may be termed a gate xe2x80x9cbus-barxe2x80x9d or gate xe2x80x9crunnerxe2x80x9d structure. A simple construction is possible in which the thick trench-etch mask area provides at least the bulk of the insulation needed between the gate bus-bar and the underlying high-doped end region. Nonetheless, when the device termination additionally includes a field insulator, an area of the field insulator may be incorporated also under the trench-mask as extra insulation between the metal track and the underlying high-doped end region.
In another scenario, the respective end structure extends around the perimeter of the cellular device area as a device termination. Thus, inter alia, there can be achieved advantageous modifications of the device termination schemes disclosed in JP-A-2001-24193. In this scenario, the high-doped end region may have an outer perimeter that terminates in a field insulator onto which the trench-etch mask extends. An outwardly-extending field-plate may extend over the field insulator, over a part of the drain region outside the outer perimeter of the end region. This field-plate can be connected to the trench-gate via the conductive-layer connection at the end trench.
The trench-etch mask area may be composed of a single insulating material. Preferably, a multiple-layer composition of different materials is used, which can provide insulation of a high integrity and of a reduced susceptibility to etching or other degradation during the device processing stages. Thus, for example, the trench-etch mask may comprise a thick layer of silicon nitride on a thin stress-relieving layer of silicon dioxide. A further layer of silicon dioxide may be present on the thick nitride layer as a part of the intermediate insulating layer.
The gate dielectric of the device may comprise a thin thermally grown oxide, and/or it may comprise a deposited layer. In this latter case, an area of the deposited gate dielectric layer can be present on the area of the trench-etch mask below the conductive layer thereon.
The trench-etch mask generally comprises a thick layer of deposited material, advantageously silicon nitride, which (as described in detail below) has less of a dopant-depletion effect on the underlying high-doped end region than does the thermal growth of a thick oxide. This thick silicon nitride mask area can be incorporated into the device termination structure to avoid growing a thick field oxide. If a thick oxide is included as a field insulator, this oxide is preferably deposited. In a particularly advantageous and compact termination structure, the thick deposited insulator may be accommodated within a deeper, wide field trench at the outer perimeter of the termination region of the second conductivity type. The trench-etch mask may extend directly on this oxide-filled termination trench.
According to a second aspect of the present invention, there is provided a method of manufacturing a cellular trench-gate semiconductor device having one or more end structures (for example, for a gate bus-bar and/or device termination) in accordance with the first aspect. Such a method preferably includes the process steps set out in claim 18. The gate material may be patterned to define the conductive layer on the trench-etch mask. Thereafter, the trench-etch mask and its windows may be used to provide device features (for example, the source region and/or an insulating capping layer on the trench-gate) in a self-aligned manner with respect to the gate trench.
The present invention is compatible with self-alignment techniques of the advantageous manufacturing method disclosed in U.S. Pat. No. 6,087,224 (our reference PHB34245). In this method, sidewall extensions (spacers) are provided at the trench-etch mask windows and are used for self-alignment processing at different stages. By this means, narrow trench-gates can be formed (narrower than the window), and the source region and a contact window for a source electrode can be determined in a self-aligned manner with respect to this narrow trench. The whole contents of U.S. Pat. No. 6,087,224 are hereby incorporated herein as reference material.